Professional Development Course on VLSI - ASIC Synthesis, Static Timing Analysis and Design for Testability (Full-time)

Sandeepani offers the 20-week (Monday - Friday) Professional Development Course for recent graduates and post-graduates in Electronics/Electrical/Telecommunication engineering. This program is specifically designed with an objective to provide a sound platform for the students and prepare them for a successful career in the fields of ASIC and FPGA Verification.
The PDC offers the right blend of classroom teaching, quality hands-on training from 'concept-to-project', covering design methodology using industry standard tools and practices. The course includes a project work as well.
Placement assistance is provided to those who complete all modules of this course and a pre-placement test.

Course Duration: 20 Weeks

Course Structure and Outline


Module Title

What You Learn



  • Linux operating system - file system and commands
  • Python Scripting


Advanced Digital System Design

  • Number Systems
  • Logic Gates
  • Boolean Expressions
  • Combinational Circuits
  • Introduction to Registers and Counters
  • Synchronous Finite State Machine Design
  • Data-path elements - Arithmetic Structures
  • Introduction to Programmable Platforms
  • Design Capture and Simulation
  • Practical Digital System Design Examples



  • Hardware Modeling Overview
  • Verilog language concepts
  • Modules and Ports
  • Operators, Dataflow Modeling
  • Introduction to Test benches
  • Procedural Statements
  • Coding for Finite State Machines
  • Coding For Synthesis
  • Tasks and Functions
  • Advanced Verilog Test benches


FPGA Design and Debugging

  • FPGA Architecture - Basic Components of FPGA (LUT, CLB, Switch Matrix, IOB), FPGA Architecture of different families: 7-series and UltraScale devices, Zynq
  • FPGA Design Flow - Xilinx Vivado tool Flow, Reading Reports, Implementing IP cores, Debugging Using Vivado Analyzer
  • Optimal FPGA Design - HDL Coding Techniques for FPGA, FPGA Design Techniques, Synthesis Techniques, Implementation Options
  • Static Timing Analysis - Global Timing Constraints, Path specific timing constraints, Achieving Timing Closure, Introduction to Reset techniques, Clock Domain Crossing, Multiple Clock Domains


ASIC Synthesis

  • Introduction to Synthesis
  • Constraining Design for timing area and power
  • Understanding and Exploring .lib
  • Logical and Physical Library
  • Synthesize Design
  • Wire Load Models
  • Timing Checks
  • Report, Analyze and debug results
  • Optimization Techniques
  • Fattening and Structuring
  • Removing Hierarchy and Optimizing Clock Networks


Static Timing Analysis

  • STA overview and concepts
  • Clocking - Handling clock muxes, clock dividers
  • Generated clocks, Clocking Exceptions
  • Timing Exceptions
  • Analysing Timing Reports
  • Timing Challenges
  • Steps to achieve Timing Closure
  • Cell Swapping
  • Bottleneck Analysis
  • Clock Gating Checks
  • Case Analysis
  • Environment and Constraints


Design for Testability

  • DFT Overview
  • DFT Flow
  • Understanding of Defects and Faults
  • Functional test Vs Structural Test
  • Types of DFT
  • Memory BIST and Logic BIST
  • Boundary Scan DFT
  • Scan Insertion
  • Scan Chain Reordering
  • Test pattern generation
  • Scan Insertion Using Tessent Scan
  • ATPG Using Tessent FastScan
  • Configuring Scan Chains
  • Test Patterns and Test Patterns Generation
  • Advanced Fault Models and Complex Pattern Generation
  • Hands-On Labs

Integrated in the course

Course Project

  • Design/DFT/Implementation

1) The contents listed above is a representative outline and is subject to change at short notice in compliance with the current industry demands.

2) Legend: P# - Primer Module, C# - Core Module

Download course brochure here.

Need More Info ?

Contact us : (+91) 72597 87866 and (+91) 98441 82555

Email us :

Admission Office:

(080) 4197 0445

Front Office:

(080) 4197 0400