Course Duration: 20 Weeks |
Course Structure and Outline |
Mod. |
Module Title |
What You Learn |
P1 |
Orientation |
- Linux operating system - file system and commands
- Python Scripting
|
P2 |
Advanced Digital System Design |
- Number Systems
- Logic Gates
- Boolean Expressions
- Combinational Circuits
- Introduction to Registers and Counters
- Synchronous Finite State Machine Design
- Data-path elements - Arithmetic Structures
- Introduction to Programmable Platforms
- Design Capture and Simulation
- Practical Digital System Design Examples
|
P3 |
Verilog |
- Hardware Modeling Overview
- Verilog language concepts
- Modules and Ports
- Operators, Dataflow Modeling
- Introduction to Test benches
- Procedural Statements
- Coding for Finite State Machines
- Coding For Synthesis
- Tasks and Functions
- Advanced Verilog Test benches
|
P4 |
FPGA Design and Debugging |
- FPGA Architecture - Basic Components of FPGA (LUT, CLB, Switch Matrix, IOB), FPGA Architecture of different families: 7-series and UltraScale devices, Zynq
- FPGA Design Flow - Xilinx Vivado tool Flow, Reading Reports, Implementing IP cores, Debugging Using Vivado Analyzer
- Optimal FPGA Design - HDL Coding Techniques for FPGA, FPGA Design Techniques, Synthesis Techniques, Implementation Options
- Static Timing Analysis - Global Timing Constraints, Path specific timing constraints, Achieving Timing Closure, Introduction to Reset techniques, Clock Domain Crossing, Multiple Clock Domains
|
C1 |
ASIC Synthesis |
- Introduction to Synthesis
- Constraining Design for timing area and power
- Understanding and Exploring .lib
- Logical and Physical Library
- Synthesize Design
- Wire Load Models
- Timing Checks
- Report, Analyze and debug results
- Optimization Techniques
- Fattening and Structuring
- Removing Hierarchy and Optimizing Clock Networks
|
C2 |
Static Timing Analysis |
- STA overview and concepts
- Clocking - Handling clock muxes, clock dividers
- Generated clocks, Clocking Exceptions
- Timing Exceptions
- Analysing Timing Reports
- Timing Challenges
- Steps to achieve Timing Closure
- Cell Swapping
- Bottleneck Analysis
- Clock Gating Checks
- Case Analysis
- Environment and Constraints
|
C3 |
Design for Testability |
- DFT Overview
- DFT Flow
- Understanding of Defects and Faults
- Functional test Vs Structural Test
- Types of DFT
- Memory BIST and Logic BIST
- Boundary Scan DFT
- Scan Insertion
- Scan Chain Reordering
- Test pattern generation
- Scan Insertion Using Tessent Scan
- ATPG Using Tessent FastScan
- Configuring Scan Chains
- Test Patterns and Test Patterns Generation
- Advanced Fault Models and Complex Pattern Generation
- Hands-On Labs
|
Integrated in the course |
Course Project |
- Design/DFT/Implementation
|
