Course Duration: 16 Weeks |
Course Structure and Outline |
Mod. |
Module Title |
What You Learn |
P1
(5 Days) |
Engineering primer |
- Number systems
- Logic gates
- Boolean expressions
- Introduction to registers and counters
- Introduction to Embedded systems
|
C1
(10 Days) |
Advanced Digital System Design |
- Synchronous Finite State Machine Design
- Data-path elements – Arithmetic Structures
- Introduction to Programmable Platforms
- Design Capture and Simulation
- Practical Digital System Design Examples
|
C2
(20 Days) |
Verilog |
- Hardware Modeling Overview,
- Verilog language concepts
- Modules and Ports
- Dataflow Modeling
- Introduction to Test benches
- Operators
- Procedural Statements
- Controlled Operation Statements
- Coding for Finite State Machines
- Coding For Synthesis
- Tasks and Functions
- Advanced Verilog Test benches
|
C3
(15 Days) |
FPGA Design |
- FPGA Architecture - Basic Components of FPGA (LUT, CLB, Switch Matrix, IOB), FPGA Architecture of different families: 7-series and UltraScale devices, Zynq
- FPGA Design Flow – Xilinx Vivado tool Flow, Reading Reports, Implementing IP cores, Debugging Using Vivado Analyzer
- Optimal FPGA Design – HDL Coding Techniques for FPGA, FPGA Design Techniques, Synthesis Techniques, Implementation Options
- Static Timing Analysis – Global Timing Constraints, Path specific timing constraints, Achieving Timing Closure, Introduction to Reset techniques, Clock Domain Crossing, Multiple Clock Domains
|
Integrated in the course |
Course Project |
|
Elective 1
(15 Days) |
Functional Verification with SystemVerilog |
- Introduction to Verification and Verification Plan
- Verification Tools
- Stimulus and Response
- SystemVerilog Basics – Introduction to SystemVerilog, Enhancement made in SystemVerilog over Verilog, Interface and Modports
- Introduction to Bus Functional Models
- Verification environment and its components
- SystemVerilog for Verification - SystemVerilog Event Ordering, Clocking block and Program block, OOP's Concept of SystemVerilog - Parameterized classes, Virtual interface, Constrained Randomization techniques, Functional Coverage (Coverage Driven Verification), SystemVerilog Assertions
|
Elective 2
(10 Days) |
UVM |
- Introduction to UVM
- UVM Classes
- UVM Factory
- Sequence Item, Sequencer, Virtual Sequences
- Transaction Level Modeling
- UVM Reporting Methods
- Development of Reusable Verification Environment
|
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