Course Name (click on course name below for details) | Choose Date | Duration | Registration |
Introduction to Zynq UltraScale+ MPSoC Architecture | 10am - 1pm IST | ||
Introduction to FPGA Design flow using Vivado | 10am - 1pm IST | ||
Hardware Debugging using Vivado | 10am - 1pm IST | ||
Introduction to Dynamic Functional eXchange (Partial Reconfiguration) | 10am - 1pm IST | ||
Introduction to Versal | 10am - 1pm IST | ||
Designing with Vivado IP Integrator | 10am - 1pm IST | ||
Introduction to High Level Synthesis | 10am - 1pm IST | ||
AMD Versal for Beginners | 10am - 5pm IST |
Contact us:
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Email us: training@coreel.com
Admission Office:
(080) 4197 0445
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